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| SL74HCT573 Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS The SL74HCT573 is identical in pinout to the LS/ALS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled. * TTL/NMOS-Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A ORDERING INFORMATION SL74HCT573N Plastic SL74HCT573D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 20=VCC PIN 10 = GND Output Enable L L L H Latch Enable H H L X D H L X X Output Q H L no change Z X = don't care Z = high impedance SLS System Logic Semiconductor SL74HCT573 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 35 75 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HCT573 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 0.1 0.5 85 C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 1.0 5.0 125 C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 1.0 10 A A V Unit VIH VIL VOH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 6.0 mA 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 V V V VOL Maximum Low-Level Output Voltage VIN= VIL or VIH IOUT 20 A VIN= VIL or VIH IOUT 6.0 mA IIN IOZ Maximum Input Leakage Current Maximum Three State Leakage Current VIN=VCC or GND Output in High-Impedance State VIN =VIH or VIL VOUT=VCC or GND VIN=VCC or GND IOUT=0A VIN=2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0A ICC Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current 5.5 4.0 40 160 A ICC -55C 25C to 125C 2.4 mA 5.5 2.9 SLS System Logic Semiconductor SL74HCT573 AC ELECTRICAL CHARACTERISTICS(VCC =5.0 V 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol tPLH, t PHL tPLH, t PHL tPLZ, t PHZ tPZH, t PZL tTLH, t THL CIN COUT Parameter Maximum Propagation Delay, Input D to Q (Figures 1 and 5) Maximum Propagation Delay,Latch Enable to Q (Figures 2 and 5) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximu m Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Output Transition Time, Any Output (Figures 1 and 5) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Enabled Output) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 25 C to -55C 30 30 28 28 12 10 15 85C 38 38 35 35 15 10 15 125C 45 45 42 42 18 10 15 Unit ns ns ns ns ns pF pF Typical @25C,VCC=5.0 V 48 pF TIMING REQUIREMENTS (VCC =5.0 V 10%, CL=50pF,Input t r=tf=6.0 ns) Guaranteed Limit Symbol tSU Parameter Minimum Setup Time, Input D to Latch Enable (Figure 4) Minimum Hold Time, Latch Enable to Input D (Figure 4) Minimum Pulse Width, Latch Enable (Figure 2) Maximum Input Rise and Fall Times (Figure 1) 25 C to -55C 10 85C 13 125C 15 Unit ns th 5 5 5 ns tw tr, tf 15 500 19 500 22 500 ns ns SLS System Logic Semiconductor SL74HCT573 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms EXPANDED LOGIC DIAGRAM Figure 5. Test Circuit Figure 6. Test Circuit SLS System Logic Semiconductor SL74HCT573 SLS System Logic Semiconductor |
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